STM32_STEmWin_1

PART I. HARDWARE CONFIGURATION

Acquire tools

Cause this is not the point of this article all steps will be described briefly.

STM32CubeMX

The first tool that we need is some kind of code/board configurator - STM32CubeMX. You should download it here .
In exchange for this free tool STM will ask for your e-mail.
Present version is 4.15.1 and archive name is en.stm32cubemx.zip. Linux and Win installation files both are in this archive.
To start this tool after installation under Linux:
 ~/STM32CubeMX/STM32CubeMX 

Libraries

Examples, drivers and middleware you can take here . Last version on present moment is 1.4.0, archive has name en.stm32cubef7.zip.

"I"DE

Some words before we begin. You should understand that Eclipse is a completely unprofessional tool for ARM development. It does not work out-of-the-box. Its linker's (gcc's linker) work is completely unexplainable.
I use Keil on my work. It is fast, easy and reliable, but its price is insane. So you should be patient and follow the instructions. If something of after-mentioned installation process does not work for you, look forums, use Google.
Eclipse for Ubuntu you can find here . I advise you to take this ready package and not to try to install it from package. Just unpack it and add some crutches. There is no installation process, just unpack and run.
Before you run Eclipse you should add some environment variable:
export SWT_GTK3=0
Then open eclipse.ini file and add these lines:
--launcher.GTK_version
2
before the line:
--launcher.appendVmargs
Additional info about this issue look here .
After that, you will be able to install plugin for STLink. Receipt how to install System Workbench plugin in Eclipse, look here . But openocd will not work. If you try, you will receive some unexplainable errors about absence of libhidapi-hidraw.so.0.
So you should install openocd:
sudo apt-get install openocd
If you have some issues with Java, reinstall it, following next steps:
sudo apt-get update
sudo apt-get upgrade
sudo apt-get autoremove
sudo apt-get purge openjdk-\*
sudo rm -rf /usr/local/java
sudo mkdir /usr/local/java 
#here should be path to your jre-8u91-linux-x64.tar.gz: cd ~/Java
sudo cp -r jre-8u91-linux-x64.tar.gz /usr/local/java cd /usr/local/java sudo chmod a+x jre-8u91-linux-x64.tar.gz sudo tar zxvf jre-8u91-linux-x64.tar.gz

Open '/etc/profile' file:
sudo nano /etc/profile
and add the next lines to the end of this file:
JAVA_HOME=/usr/local/java/jre1.8.0_91
PATH=$PATH:$HOME/bin:$JAVA_HOME/bin
export JAVA_HOME
export PATH
And final steps:
sudo update-alternatives --install "/usr/bin/java" "java" "/usr/local/java/jre1.8.0_91/bin/java" 1
sudo update-alternatives --set java /usr/local/java/jre1.8.0_91/bin/java
sudo update-alternatives --set javaws /usr/local/java/jre1.8.0_91/bin/javaws
. /etc/profile
java -version
Here some drunk guy made article by theme. So good luck.

Configure HAL library for STM32F746G DISCO

It is possible that you don't want to tinker in hardware.
In this case you can copy ready project,
presented in the end of this article,
put it in some '*.txt' file and change its extension to '*.ioc'
and don't read all below-mentioned.
In CubeMX press button 'new project', then in board selector find Discovery-type STM32F746G DISCO board.

Let's configure project for our board.

FMC

FMC means Flexible Memory Controller, look here for details. According to DISCO's datasheet (look for document UM1907 ), we have 128-Mbit SDRAM(Synchronous dynamic random-access memory) from MICRON:

Connection:
MCU's pin FMC_SDCKE0 [L4] connected to CKE [J2] SDRAM's pin - clock enable. This signal activates (HIGH) and deactivates (LOW) the CLK signal.
MCU's pin FMC_SDNE0 [J4] connected to CS# [J8] SDRAMS'pin - chip select. This signal enables (registered LOW) and disables (registered HIGH) the command decoder (commands to pins CAS#, RAS# and WE#).
So inside FMC's subsection 'Clock and chip enable' we should select configuration 'SDCKE0-SDNE0':
'CUBEMX' -> Pinout -> FMC -> SDRAM1 -> SDCKE0-SDNE0
And check that pins [L4] and [J4] of MCU-s BGA array became colored in green.
Accordingly to Micron's SDRAM datasheet , it has 4 internal banks, every bank has 4096 rows.
Banks selected through pins BA1 and BA0. MCU's pin FMC_NBL0 [N12] connected to BA0 [J7] SDRAM's pin and MCU's pin FMC_NBL1 [N11] connected to BA1 [H8] SDRAM's pin.
So after you select inside FMC's subsection 'internal bank number' bank quantity 4:
'CUBEMX' -> Pinout -> FMC -> SDRAM1 -> Internal bank number -> 4 banks,
you should see pins [N11] and [N12] became green.
If we want to have access to every bank's row we should use 12-lines of parallel protocol.
4096 = 2^0 + 2^1 + 2^2 + ... + 2^10 + 2^11.
Hardware connection will look like:
MCU's pin SDRAM's pin
FMC_A0 [D2] A0 [G8]
FMC_A1 [E2] A1 [G9]
FMC_A2 [G2] A2 [F7]
FMC_A3 [H2] A3 [F3]
FMC_A4 [J2] A4 [G1]
FMC_A5 [K3] A5 [G2]
FMC_A6 [M6] A6 [G3]
FMC_A7 [N6] A7 [H1]
FMC_A8 [P6] A8 [H2]
FMC_A9 [M8] A9 [J3]
FMC_A10 [N7] A10 [G7]
FMC_A11 [M7] A11 [H9]
Every bank has 256 column x 4096 raws, every cell has 32 bits. Every bit in cell is accessed through corresponding SDRAM's DQ* pin. Because only 16 data lines of 32-lines data bus are used (data lines from 16 to 31 permanently 0):

we can access only 64-Mbit:
4 x (4096x256) x 16 = 67'108'864 == 64 x 1024 x 1024
To make such connection possible we should permanently mask write and read access with 0b1111'1111' 1111'1111' 0000'0000' 0000'0000. It is made by pulling down SDRAM's pins DQM2[F8] and DQM3[F2].
But SDRAM's pins DQM0 and DQM1 are connected to MCU's pins FMC_NBL0[A6] and FMC_NBL1[A5] correspondingly.
These pins become usable after you selected '16-bit byte enable' inside FMC's subsection 'Byte enable'.
This wasting of pins (you may ask why we couldn't just pull up these pins) is connected with SDRAM protocol's peculiarity:
"The DQM signal must be de-asserted prior to the WRITE command to ensure that the written data is not masked." /Micron's SDRAM datasheet /
And as you had already seen 16 data lines have next connection:
MCU's pin SDRAM's pin
FMC_D0 [L12] DQ0 [R8]
FMC_D1 [K13] DQ1 [N7]
FMC_D2 [B12] DQ2 [R9]
FMC_D3 [C12] DQ3 [N8]
FMC_D4 [R8] DQ4 [P9]
FMC_D5 [N9] DQ5 [M8]
FMC_D6 [P9] DQ6 [M7]
FMC_D7 [R9] DQ7 [L8]
FMC_D8 [P10] DQ8 [L2]
FMC_D9 [R10] DQ9 [M3]
FMC_D10 [R12] DQ10 [M2]
FMC_D11 [P11] DQ11 [P1]
FMC_D12 [R11] DQ12 [N2]
FMC_D13 [L15] DQ13 [R1]
FMC_D14 [L14] DQ14 [N3]
FMC_D15 [K15] DQ15 [R2]
And finally I should mention command lines:
MCU's pin SDRAM's pin
CAS# [K7] FMC_SDNCAS [B7]
RAS# [J9] FMC_SDNRAS [P8]
WE# [K8] FMC_SDNWE [J3]
These lines define commands for SDRAM:

In 'CUBEMX' final configuration will look like:

SDRAM Timings

Common routine to set SDRAM's timings will be the next:
1 - Find what clock goes to FMC;
2 - Find how FMC divides it;
3 - Find required delays from SDRAM's datasheet;
4 - Recalculate delays in 'ns' to clock cycles.
So let's move step by step.
For the beginning, from this source (look page 20) , we will find:

HCLK is an internal AHB clock frequency:

AHB(Advanced High-performance Bus) together with APB(Advanced Peripheral Bus) are forming (connection between Buses is performing by Bus Bridge) AMBA(Advanced Microcontroller Bus Architecture). This is main bus that connects Cortex's processor with memory, debug and peripheral devices.
From MICRON's SDRAM datasheet we can find, that installed in STM32F746G DISCO, is PC-100 type.
This means that it has 100MHz command rate (commands forms by sending signals to CAS#, RAS# and WE# SDRAM's pins).
So let's set 'HCLK' to 200MHz:

And in FMC configuration, let's set FMC clock divider to 2HCLK clock for one FMC clock:

This means that now FMC will operate on 100MHz frequency, and one clock cycle will take 10ns.
Now let's find in MICRON's SDRAM datasheet next timings:
1) Load mode register to active delay - this means required delay before command ACTIVE, after issuing command LOAD MODE REGISTER (LMR).
This delay appears, because there is some time required after SDRAM chip configuration changes, caused by LMR command, to take effect.
From MICRON's SDRAM datasheet , table 13, we will find:

Accordingly to MICRON's SDRAM datasheet , p.37:
"The mode register defines the specific mode of operation ...
The mode register is programmed via the LOAD MODE REGISTER command and retains the stored information until it is programmed again or the device loses power.
...
Simply speaking we load configuration information in SDRAM by address lines, and after that we should wait 2 cycles. After this period configuration will take effect.
The mode registers must be loaded when all banks are idle, and the controller must wait MRD before initiating the subsequent operation."
2) Exit self-refresh delay - this time required for SDRAM exits from low-power self-refresh mode.
From MICRON's SDRAM datasheet , table 12, we will find:

70ns means 7 FMC clock cycles
Accordingly to MICRON's SDRAM datasheet , p.74:
"The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH.
After CKE is HIGH, the device must have NOP commands issued for a minimum of two clocks for XSR because time is required for the completion of any internal refresh in progress."
3) Self refresh time. Accordingly to document RM0385 , p.368:
"The SDRAM device must remain in Self-refresh mode for a minimum period of time of TRAS and can remain in Self-refresh mode for an indefinite period beyond that."
SDRAM timing register of FMC controller has next offset: 0x148 + 4 * (x – 1), where x could be 1 or 2. In our case, we have one SDRAM chip, it will be 0x148 (look further in code).
And control bits, to set this minimum time, are:

Accordingly to MICRON's SDRAM datasheet , p.74:
"After self refresh mode is engaged, the device provides its own internal clocking, enabling it to perform its own AUTO REFRESH cycles. The device must remain in self refresh mode for a minimum period equal to RAS and remains in self refresh mode for an indefinite period beyond that."
RAS period is:

Let's try to make it 40ns, that means 4 FMC clock cycles.
I found how it works in code finally generated by 'CUBEMX'.
There will be function that will initialize FMC controller:
HAL_SDRAM_Init(&hsdram, &SDRAMTiming)
'&SDRAMTiming' is the address of structure, that is type of 'FMC_SDRAM_TimingTypeDef'. This type of structure has next member:
typedef struct
{
...
uint32_t SelfRefreshTime; /* Defines the minimum Self Refresh period in number of memory clock */
...
}FMC_SDRAM_TimingTypeDef;
Inside function 'HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)' there will be initialization part:
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
...
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 
...
}
This function makes next arrangement:
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
...
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1)|\
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
(((Timing->SelfRefreshTime)-1) << 8)|\
(((Timing->RowCycleDelay)-1) << 12)       |\
(((Timing->WriteRecoveryTime)-1) <<16)|\ (((Timing->RPDelay)-1) << 20)|\
(((Timing->RCDDelay)-1) << 24));
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
...
}
This means that 'SelfRefreshTime' will be written into 'SDTR' register.
Inside file 'stm32f756xx.h' (CMSIS driver) you will find what 'SDTR' is:
typedef struct
{
...
__IO uint32_t SDTR[2];        /* SDRAM Timing registers, Address offset: 0x148-0x14C */
...
} FMC_Bank5_6_TypeDef;
And next bit definition:
/******************  Bit definition for FMC_SDTR1 register  ******************/
...
#define  FMC_SDTR1_TRAS                     0x00000F00U        /* TRAS[3:0] bits (Self refresh time) */
#define  FMC_SDTR1_TRAS_0                   0x00000100U        /* Bit 0 */
#define  FMC_SDTR1_TRAS_1                   0x00000200U        /* Bit 1 */
#define  FMC_SDTR1_TRAS_2                   0x00000400U        /* Bit 2 */
#define  FMC_SDTR1_TRAS_3                   0x00000800U        /* Bit 3 */
....
4) SDRAM common row cycle delay - as I can understand this is delay between access from current row to next row.
To 'open' row you should issue ACTIVE command, (send signals to pins BA0...BA1, to row address pins A0-A11 and code to pins CAS#,RAS# and #WE). So from MICRON's SDRAM datasheet , table 12, we will find:

So let's make this delay equal to 6 FMC clock cycles.
//I tried to do it equal to 7, but in this case 'CUBEMX' requires to make timing Write recovery time equals to 3. But if you open file:
$Library_path\STM32Cube_FW_F7_V1.4.0\Drivers\BSP\STM32746G-Discovery\stm32746g_discovery_sdram.c,
at line 149 you will find next timings:
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
...
Timing.RowCycleDelay = 7;
...
I think this is some kind of bug. I can't find any sane explanation for this.
But in the SDRAM example in the same library, in file:
$Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Examples\FMC\FMC_SDRAM\Src\,
at line 119 you will find next declaration:
/* SDRAM device configuration */
...
SDRAM_Timing.RowCycleDelay = 6;
....
Anyway both timings work perfect.
5) Write recovery time, as I understand, it is required delay after write data to SDRAM:

Let's make it equal 2 FMC clock cycles.
6) SDRAM common row precharge delay requires 2 FMC clock cycles:

As I understand it, it is the required term after PRECHARGE command and any other command.
7) Row to column delay as I can understand, is the delay after ACTIVE command issue and command to read/write from certain column inside raw, from SDRAM's datasheet, I found:

That means it requires 2 FMC clock cycles.

SDRAM Control

Column bit number, Row bit number

Cause each of 4096 rows of the single SDRAM's BANK consists of 256 cells, we need 8 bits to access each of this cell(column):

CAS latency

Accordingly to MICRON's SDRAM datasheet , p.41, the CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be configured like two or three clocks.
I choose two clocks:

SDRAM common read pipe delay

It was really hard to find what STM's engineers meant in this definition. But in HAL library, in file 'stm32f7xx_II_fmc.h' I found definition of structure type 'FMC_SDRAM_InitTypeDef', in which next member is presented:
uint32_t ReadPipeDelay; /* Define the delay in system clock cycles on read data path */
Accordingly to MICRON's SDRAM datasheet , p.1:
"Internal pipelined operation; column address can be changed every clock cycle".
So I set this parameter to 0:

So finally all this configuration will look in 'CUBEMX' like:

And 'CUBEMX' will create next function in your 'main.c' file:
void MX_FMC_Init(void){
			FMC_SDRAM_TimingTypeDef SdramTiming;
	hsdram1.Instance = FMC_SDRAM_DEVICE; //look end of this article for explanation
	hsdram1.Init.SDBank = FMC_SDRAM_BANK1; /*Specifies the SDRAM memory device that will be used */
	hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; /* Defines the number of bits of column address */
	hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; /* Defines the number of bits of row address */
	hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; /* Defines the memory device width */
	hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; /* Defines the number of the device's internal banks */
	hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1; /*Defines the SDRAM CAS latency in number of memory clock cycles */
	hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; /* Enables the SDRAM device to be accessed in write mode */
	hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; /* Define the SDRAM Clock Period for both SDRAM devices and they allow to disable the clock before changing frequency */
	hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; /* This bit enable the SDRAM controller to anticipate the next read commands during the CAS latency and stores data in the Read FIFO */
	hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; /* Define the delay in system clock cycles on read data path */
			/* SdramTiming */
	SdramTiming.LoadToActiveDelay    = 2;
	SdramTiming.ExitSelfRefreshDelay = 7;
	SdramTiming.SelfRefreshTime      = 4;
	SdramTiming.RowCycleDelay        = 6; /* Defines the delay between the Refresh command and the Activate command and the delay between two consecutive Refresh commands in number of memory clock cycles */
	SdramTiming.WriteRecoveryTime    = 2;
	SdramTiming.RPDelay              = 2; /* Defines the delay between a Precharge Command and an other command in number of memory clock cycles */
	SdramTiming.RCDDelay             = 2;
	HAL_SDRAM_Init(&hsdram1, &SdramTiming);
}
In this code 'hsdram1' is a structure of type 'FMC_SDRAM_InitTypeDef' that configures 'FMC' for current 'SDRAM' type. This type of structure is declared in 'stm32f7xx_II_fmc.h'.
At the end of this article I explained relationship between CMSIS and HAL and how this code works.

System clock

There are two clock sources connected to MCU on STM32F746G DISCO:
- the first is a clock crystal X3 connected to RCC_OSC32_IN [E1] and RCC_OSC32_OUT [F1] MCU's pins;
- the second is a 25.00 MHz frequency generator X2 connected to RCC_OSC_IN [G1] pin.
Schematic looks like:

In 'CUBEMX' these crystals are initializing by:

For clock configuration I took ready configuration from LTDC example: $Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Examples\LTDC\LTDC_Display_1Layer\Src\main.c
Look for functions:
void SystemClock_Config(void){
	...
	/* Enable HSE Oscillator and activate PLL with HSE as source */
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
	RCC_OscInitStruct.PLL.PLLM = 25;
	RCC_OscInitStruct.PLL.PLLN = 400;  
	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
	...
} 
and
int main(void)
{
	...  
	/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
	PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
	PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
	PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
	PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
	...
} 
And make the same config in 'CUBEMX':
Main chain is here:
Input frequency 25MHz from X2 generator -> PLL Source Mux - switch to HSE -> PLLM == /25 -> PLLSAI1.PLLSAIN == X192 -> PLLSAI1.PLLSAIR == /5 -> PLLSAIRDiv = /4 -> 9.6MHz to LCD-TFT. BUT!
You will find other clock configurations for USB_HS in part 2 of this article, and for 'STEmWin' in part 4 of this article.

LTDC

STM32F746G DISCO has a TFT(thin-film transistor) 4.3-inch display, produced by ROCKTECH. Model name is RK043FN48H-CT672B. This part is especially customized for STM.
I want to make a break and say some words about ROCKTECH. This company is really good. I wrote them a letter asking for a datasheet for this display. (I can send it to you if you ask) They responded very quickly and provided the data sheet to me without any additional questions. ROCKTECH produces wide range of displays, and part, that is presented on DISCO as I think, is not the best of them. I'm looking for my further design for 10.1" 1280x800px part - RK101II01D. This part is really awesome. Price is really low (about 30-40$), quality you can test by yourself, and they can provide you samples for test design.
So let's continue.
Our display RK043FN48H-CT672B has next pinout:

There are 24 data lines, so we select 'RGB888(24bits)' in 'LTDC' section of 'CUBEMX'.

LCD connection

Next pins will be connected:
Display connection
Red data Green data Blue data Protocol
MCU's pin LCD's pin MCU's pin LCD's pin MCU's pin LCD's pin MCU's pin LCD's pin
LCD_R0 [G4] 5 LCD_G0 [J12] 13 LCD_B0 [J12] 21 LCD_DISP [E3] 31
LCD_R1 [R6] 6 LCD_G1 [H12] 14 LCD_B1 [B9] 22 LCD_DE [C4] 34
LCD_R2 [R7] 7 LCD_G2 [J13] 15 LCD_B2 [C9] 23 LCD_HSYNC [D5] 32
LCD_R3 [P7] 8 LCD_G3 [H13] 16 LCD_B3 [D10] 24 LCD_VSYNC [E4] 33
LCD_R4 [N8] 9 LCD_G4 [G12] 17 LCD_B4 [C7] 25 LCD_CLK [H3] 30
LCD_R5 [M9] 10 LCD_G5 [G13] 18 LCD_B5 [D7] 26 LCD_INT [G3] 38
LCD_R6 [M14] 11 LCD_G6 [F12] 19 LCD_B6 [C6] 27 LCD_SCL [N13] 39
LCD_R7 [K12] 12 LCD_G7 [F13] 20 LCD_B7 [C5] 28 LCD_SDA [P14] 40
LCD's RESET pin connected to MCU's NRST [J1] pin and all of them are connected to black push button.
LCD's backlight anode and cathode (pin 1 and 2) are connected to STLD40D module - white LED power supply (regulated by current boost converter) for large display backlight. Accordingly to STLD40D's datasheet , pull down resistor on its FB pin defines supply current. For 10Om it will be 15mA; pull down resistor on Rset line limits current flowing through inductor, for installed on DISCO 100kOm it will be the lowest 200mA (look sheet 13 of UM1907 )
As you could mention, backlight module has EN pin connected to MCU's LCD_BL_CTRL [D8]. High state on this line enables IC's operation. Additionally pin ENABLE can be used to dim the LED by applying a low frequency PWM signal.
Last 5 pins of LCD 40-pin connector (3, 4, 29, 35, 36) are connected to VDD (3.3V) and GND.
Inside 'CUBEMX' you should switch bookmark to 'Configuration' and set up LCD driver.

LCD timings

Accordingly to RK043FN48H-CT672B data sheet timings should be:

So let's make corresponding configuration of our LCD in 'CUBEMX':

I tried such configuration in the example provided by STM - $Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Examples\LTDC\LTDC_Display_1Layer
In file 'main.c' I changed:
static void LCD_Config(void)
{ 
	...
	/* Timing Configuration */
	hltdc_F.Init.HorizontalSync = 0;
	hltdc_F.Init.VerticalSync = 0;
	hltdc_F.Init.AccumulatedHBP = 43;
	hltdc_F.Init.AccumulatedVBP = 12;
	hltdc_F.Init.AccumulatedActiveH = 284;
	hltdc_F.Init.AccumulatedActiveW = 523;
	hltdc_F.Init.TotalHeigh = 288;
	hltdc_F.Init.TotalWidth = 531;
	...
}
And everything works fine.
In this example 'hltdc_F' is a structure type of 'LTDC_HandleTypeDef'.
This structure has the next members:
typedef struct
{
	LTDC_TypeDef                *Instance;                // LTDC Register base address                */
		LTDC_InitTypeDef            Init;                     // LTDC parameters                           */
	LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      // LTDC Layers parameters                    */
	HAL_LockTypeDef             Lock;                     // LTDC Lock                                 */
	__IO HAL_LTDC_StateTypeDef  State;                    // LTDC state                                */
	__IO uint32_t               ErrorCode;                // LTDC Error code                           */
} LTDC_HandleTypeDef;
In this structure the second member is the initialization parameters:
typedef struct
{
	uint32_t            HSPolarity;                // configures the horizontal synchronization polarity.	This parameter can be one value of LTDC_HS_POLARITY */
	uint32_t            VSPolarity;                // configures the vertical synchronization polarity. This parameter can be one value of LTDC_VS_POLARITY */
	uint32_t            DEPolarity;                // configures the data enable polarity. This parameter can be one of value of  LTDC_DE_POLARITY */
	uint32_t            PCPolarity;                // configures the pixel clock polarity. This parameter can be one of value of LTDC_PC_POLARITY */
	uint32_t            HorizontalSync;            // configures the number of Horizontal synchronization width. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
	uint32_t            VerticalSync;              // configures the number of Vertical synchronization height. This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
	uint32_t            AccumulatedHBP;            // configures the accumulated horizontal back porch width.	This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
	uint32_t            AccumulatedVBP;            // configures the accumulated vertical back porch height. This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
	uint32_t            AccumulatedActiveW;        // configures the accumulated active width.	This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
	uint32_t            AccumulatedActiveH;        // configures the accumulated active height.	This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
	uint32_t            TotalWidth;                // configures the total width.	This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
	uint32_t            TotalHeigh;                // configures the total height. This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
	LTDC_ColorTypeDef   Backcolor;                 // Configures the background color. */
} LTDC_InitTypeDef;

Timings from examples provided by STM

Examples provided by STM offer other timings than me based on LCD datasheet. But all these settings lying between maximums and minimums provided by LCD datasheet. That is why both configurations work.
Demonstration example
In example:
$Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Demonstration\
in file:
...\Config\LCDConf.c
You can find next function:
static void LCD_LL_Init(void)
{
	...
	/* Set LCD Timings */
	hltdc.Init.HorizontalSync = (HSYNC - 1);
	hltdc.Init.VerticalSync = (VSYNC - 1);
	hltdc.Init.AccumulatedHBP = (HSYNC + HBP - 1);
	hltdc.Init.AccumulatedVBP = (VSYNC + VBP - 1);
	hltdc.Init.AccumulatedActiveH = (YSIZE_PHYS + VSYNC + VBP - 1);
	hltdc.Init.AccumulatedActiveW = (XSIZE_PHYS + HSYNC + HBP - 1);
	hltdc.Init.TotalHeigh = (YSIZE_PHYS + VSYNC + VBP + VFP - 1);
	hltdc.Init.TotalWidth = (XSIZE_PHYS + HSYNC + HBP + HFP - 1);
	...
}
These defined constants resolved in the same file as:
#define  HSYNC            ((uint16_t)41)   /* Horizontal synchronization */
#define  HBP              ((uint16_t)13)   /* Horizontal back porch      */
#define  HFP              ((uint16_t)32)   /* Horizontal front porch     */
#define  VSYNC            ((uint16_t)10)   /* Vertical synchronization   */
#define  VBP              ((uint16_t)2)    /* Vertical back porch        */
#define  VFP              ((uint16_t)2)    /* Vertical front porch       */
Such LCD timings configuration will be caused by next 'CUBEMX' configurations:
Horizontal Synchronization Width             41
Horizontal Back Porch                        13
Active Width                                 480
Horizontal Front Porch                       32
HSync Width                                  40
Accumulated Horizontal Back Porch Width      53
Accumulated Active Width                     533
Total Width                                  565
--
Vertical Synchronization Height              10
Vertical Back Porch                          2
Active Height                                272
Vertical Front Porch                         2
VSync Height                                 9
Accumulated Vertical Back Porch Height       11
Accumulated Active Height                    283
Total Height                                 285
The same timings you can find in example:
$Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Applications\STemWin\STemWin_HelloWorld,
in file:
\Src\LCDConf.c .
LTDC_Display_1Layer example
In example $Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Examples\LTDC\LTDC_Display_1Layer, in file ...\Src\main.c, in function 'static void LCD_Config(void)' you can find other timings:
/* The RK043FN48H LCD 480x272 is selected */
/* Timing Configuration */
hltdc_F.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
hltdc_F.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
hltdc_F.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
hltdc_F.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
hltdc_F.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
hltdc_F.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
hltdc_F.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
hltdc_F.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
These defined constants resolved in the file $Library_path\STM32Cube_FW_F7_V1.4.0\Drivers\BSP\Components\rk043fn48h as:
/*
*RK043FN48H Timing
*/
#define  RK043FN48H_HSYNC            ((uint16_t)41)   /* Horizontal synchronization */
#define  RK043FN48H_HBP              ((uint16_t)13)   /* Horizontal back porch      */
#define  RK043FN48H_HFP              ((uint16_t)32)   /* Horizontal front porch     */
#define  RK043FN48H_VSYNC            ((uint16_t)10)   /* Vertical synchronization   */
#define  RK043FN48H_VBP              ((uint16_t)2)    /* Vertical back porch        */
#define  RK043FN48H_VFP              ((uint16_t)2)    /* Vertical front porch       */

Touch panel

LCD has touch controller on-board - FT5336. Accordingly to 'FT5336' datasheet , this controller utilizes I2C protocol, uses 7-bit slave address, can generate interrupts and can be resetted:

Accordingly to STM32F746G DISCO datasheet touch module has the 7-bit address: 1110000(bin) == 112(dec) == 0x70(hex).
Maximum frequency is 400kHz. But 'CUBEMX' allows only 100kHz.
LCD's touch panel controller 'FT5336' connected to the MCU's I2C3, pins LCD_SCL [N13] and LCD_SDA [P14].

Final configuration should look like:

Enable Chrom-ART accelerator

Accordingly to STM32F746G datasheet (p.21):
"The Chrom-Art Acceleratorâ„¢ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion."
To initialize it:

Program/Debug

There is a ST-LINK/V2 in-circuit debuger on STM32F746G DISCO board. To activate this module in 'CUBEMX' you should make next configuration:
'System Wake-Up 4' config activates pin SYS_WKUP4 [F3] MCU's pin. This pin on current board connected to blue 'B1 User' button

--

DMA config


Such configuration is used for transferring data from one memory to another memory. This work (in code)is made by functions:
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
//In STM's DMA example it pumps 32 byte buffer stored in MCU's flash (some constant) to MCU's SRAM (some variable).
Also in future I intend to attach touch pad in project, so I add DMA for I2C3:

CRC (cyclic redundancy check) calculation unit

This unit is activated in 'CUBEMX':
CRC module is used for verifying Flash memory integrity and for Ethernet protocol, it has no use for LTDC protocol. Look here for additional info. BUT! accordingly STEmWin datasheet :

I can't find explanation how EmWin and CRC are connected.
In Segger EmWin manual I couldn't find any mention about CRC.

Additional peripheral explanation (not necessary for current project)

Digital camera interface (DCMI)

Accordingly to STM32F746G DISCO datasheet (p.42):
"The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz"
P1 connector (look for white one with black latch) has next connection to MCU:
Camera connection
MCU's pin name MCU's BGA pin # Camera connector
DCMI_D0 N14 4
DCMI_D1 P15 5
DCMI_D2 N15 6
DCMI_D3 M15 7
DCMI_D4 E13 8
DCMI_D5 C11 9
DCMI_D6 B1 10
DCMI_D7 B2 11
DCMI_PIXCLK P3 15
DCMI_HSYNC N4 17
DCMI_VSYNC D9 19
DCMI_PWR_EN E12 25
DCMI_NRST camera connector pin (#26) connected to NRST signal like LCD_RST.
NRST signal pulled up and connected to MCU's pin [J1] and all of them connected to black Reset button:
DCMI_SDA and DCMI_SCL pins are connected to MCU's [B4] and [A7] relatively.
These pins are MCU's I2C1. These pins are pulled up, and additionally connected to 14 and 15 pins of Arduino connector:
Difference between two configuration 'Slave 8 bits External Synchro' and 'Slave 8 bits Embedded Synchro':
In the second case signals DCMI_HSYNC and DCMI_VSYNC will be deactivated.
For current project I made the next settings:
...

USART

Strictly speaking you don't need USART in this project, but for debug purposes it will be very useful to have such feature. And in the second part of this article it will be necessary to make some workaround for BSP library, if you do not initialize it.
ARDUINO connector's pins 1 and 2 are connected to MCU's module USART6 ([G15] RX to pin 1 and [H15] TX to pin 2).

To initialize USART6:

After that you should make next configuration:

CUBEMX will create next function for USART6 initialization:
static void MX_USART6_UART_Init(void)
{
huart6.Instance = USART6;
huart6.Init.BaudRate = 115200;
huart6.Init.WordLength = UART_WORDLENGTH_8B;
huart6.Init.StopBits = UART_STOPBITS_1;
huart6.Init.Parity = UART_PARITY_NONE;
huart6.Init.Mode = UART_MODE_TX_RX;
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart6) != HAL_OK)
	{
	Error_Handler();
	}
}
In the end of this article I explained how such functions work.

Add USB debug

Cause project including STEmWin library is a complex enough code, I think it is useful to have some additional (to USART6) debug tools.
One of these tools is USB high speed port, that we can use like Communication Device.
I tried to use USB FULL SPEED port, but I didn't achieved success. It works good alone, but it is impossible to make it work alongside with other peripheral. I think this happens because of low quality of clock generator X2 or multi-divisional structure of consumers of its clock. But thanks to STM's engineers, they connected the second USB communication line through Microchip's PHY(Physical layer) device USB3320C-EZK . This device takes dedicated clock from X1 24MHz clock generator (same generator is a clock source for DCMI), not from main system 25MHz clock generator X2.
But even here everything is made not so good as should be. Clock generator X1 located at the other side (near camera connector) of board from PHY device (near USB ports). All this means that there are much more reasons why USB doesn't work than the possibilities that it will work.
So let's switch on USB_HS in our project:


Clock configuration that was represented in LTDC example:
$Library_path\STM32Cube_FW_F7_V1.4.0\Projects\STM32746G-Discovery\Examples\LTDC\LTDC_Display_1Layer\Src\main.c gives birth to dead USB port. After a long 'try and fail' I found only one good clock solution:
Draw your attention that clock provision line from X1 isn't represented in 'CUBEMX'. USB configuration should be:

Final configuration

Cortex M7 config


We have already initialized DMA2D (Chrome-ART Accelerator) in 'CUBEMX', but this was HAL (Hardware Abstraction Layer) drivers initialization. In this menu we initialize it in CMSIS. CMSIS (Cortex Microcontroller Software Interface Standard) is not strictly speaking a library, this is MCU's registers description made by ARM.
AXI is Advanced eXtensible Interface, part of ARM(Advanced RISC(reduced instruction set computer) Machines) AMBA(Advanced Microcontroller Bus Architecture), it is internal MCU interconnection protocol. As I understand this protocol is aimed to reduce difference in speed between fetching data from flash and MCU's core.
MPU (Memory Protection Unit) - no need in current project.
ICache - instruction cache, DCache - data cache.
Separation of instruction and data cache gives the possibility to fetch instruction and data from cache simultaneously.

HAL and CMSIS relations

If you had worked with other MCUs before ARM's (especially 8- or 16- bits), you should know that to enable or disable some peripheral or to change its configuration you should write '0'-s or '1'-s to defined registers that are a part of processor unit.
These registers have name 'SPECIAL FUNCTION REGISTERS'.
But because of quantity of these registers it becomes impossible to configure every ARM project bit by bit, like in Microchip's projects.
In this situation ARM company helps us, and creates CMSIS(Cortex Microcontroller Software Interface Standard).
CMSIS(Cortex Microcontroller Software Interface Standard) accordingly to ARM site is a vendor-independent hardware abstraction layer(HAL) for the Cortex-M processor series. In our project it is represented by file: 'stm32f746xx.h'. This file gives to STM's HAL library access to all MCU's registers. HAL just converts CMSIS in more understandable view.
For example, to configure LTDC controller there is a function 'MX_LTDC_Init()' inside 'int main(void)' in file 'main.c' This function configures LTDC controller by settling defined values in structure 'hltdc'
void MX_LTDC_Init(void)
{
	...
	hltdc.Instance = LTDC;
	hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
	hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
	hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
	hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
	hltdc.Init.HorizontalSync = 0;
	hltdc.Init.VerticalSync = 0;
	hltdc.Init.AccumulatedHBP = 43;
	hltdc.Init.AccumulatedVBP = 12;
	hltdc.Init.AccumulatedActiveW = 523;
	hltdc.Init.AccumulatedActiveH = 284;
	hltdc.Init.TotalWidth = 531;
	hltdc.Init.TotalHeigh = 288;
	hltdc.Init.Backcolor.Blue = 0;
	hltdc.Init.Backcolor.Green = 0;
	hltdc.Init.Backcolor.Red = 0;
	...
}
Structure 'hltdc' is defined in file 'main.c' as:
LTDC_HandleTypeDef hltdc;
So as I showed before briefly, structure of type 'LTDC_HandleTypeDef' has next members:
typedef struct
{
	LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */
	LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */
	LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */
	HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */
	__IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */
	__IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */
} LTDC_HandleTypeDef;
The first member of this structure is a pointer, named 'Instance' type of pointer is a structure 'LTDC_TypeDef', this type of structure is defined in file 'stm32f746xx.h' and has next members:
typedef struct{
	uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */
	__IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
	__IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
	__IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
	__IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
	__IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
	uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */
	__IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
	uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */
	__IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
	uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */
	__IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
	__IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
	__IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
	__IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
	__IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
	__IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
} LTDC_TypeDef;
So, the first, that you should do in your program, is to set address for pointer '*Instance':
hltdc.Instance = LTDC;
'LTDC' is defined in 'stm32f746xx.h' as:
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
This means, that 'LTDC' is a pointer, which points at address 'LTDC_BASE' where data type of 'LTDC_TypeDef' should be disposed. Let's find out what the address is it.
'LTDC_BASE' is defined in 'stm32f746xx.h' as:
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
'APB2PERIPH_BASE' is defined in 'stm32f746xx.h' as:
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
'PERIPH_BASE' is defined in 'stm32f746xx.h' as:
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals
So LTDC_BASE = 0x6800 + 0x00010000 + 0x40000000 = 0x40016800.
This means, that 'LTDC' is a pointer of type 'LTDC_TypeDef', that points on address 0x40016800. Description of LTDC registers you can find in document RM0385 section 18.7 on page 517.
Accordingly to this document in STM32F746 MCU program memory, data memory, registers and I/O ports are organized within the same linear 4GB address space. In the same document on page 535 you can find full LTDC registers map.
Disposition of LTDC registers:

This means, then we should settle structure of type 'LTDC_TypeDef' and write its members in defined MCU's SRAM addresses, beginning from address 0x40016800.
So let's understand what HAL is doing.
In our project, in file 'main.c' in function 'void MX_LTDC_Init(void)' we settle structure 'hltdc' and then we feed its address to function 'HAL_LTDC_Init'
HAL_LTDC_Init(&hltdc);
This function is defined in file 'stm32f7xx_hal_ltdc.c' as:
/*
* brief:  Initializes the LTDC according to the specified
*         parameters in the LTDC_InitTypeDef and create the associated handle.
* param:  hltdc: pointer to a LTDC_HandleTypeDef structure that contains
*                the configuration information for the LTDC.
* retval: HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
...
/* Configures the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
hltdc->Instance->GCR |=  (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
/* Sets Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
tmp = (hltdc->Init.HorizontalSync << 16);
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
/* Sets Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
tmp = (hltdc->Init.AccumulatedHBP << 16);
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
/* Sets Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
tmp = (hltdc->Init.AccumulatedActiveW << 16);
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
/* Sets Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
tmp = (hltdc->Init.TotalWidth << 16);
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
/* Sets the background color value */
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16);
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
...}
As you can see this function takes configuration values from structure 'hltdc' and writes it in appropriate addresses, and nothing more. Variable 'tmp' takes your parameters.

'CUBEMX' project itself

Copy this ready-to-compile project, put it in some '*.txt' file and change its extension to '*.ioc'. Run it and save in a new file (in initial state it has no necessary metadata).
#MicroXplorer Configuration settings - do not modify
CORTEX_M7.ART_ACCLERATOR_ENABLE=1
CORTEX_M7.CPU_DCache=Enabled
CORTEX_M7.CPU_ICache=Enabled
CORTEX_M7.IPParameters=ART_ACCLERATOR_ENABLE,CPU_ICache,CPU_DCache,PREFETCH_ENABLE
CORTEX_M7.PREFETCH_ENABLE=1
Dma.I2C3_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.I2C3_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C3_RX.0.Instance=DMA1_Stream2
Dma.I2C3_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C3_RX.0.MemInc=DMA_MINC_ENABLE
Dma.I2C3_RX.0.Mode=DMA_NORMAL
Dma.I2C3_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C3_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.I2C3_RX.0.Priority=DMA_PRIORITY_LOW
Dma.I2C3_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.I2C3_TX.1.Direction=DMA_MEMORY_TO_PERIPH
Dma.I2C3_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C3_TX.1.Instance=DMA1_Stream4
Dma.I2C3_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C3_TX.1.MemInc=DMA_MINC_ENABLE
Dma.I2C3_TX.1.Mode=DMA_NORMAL
Dma.I2C3_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C3_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.I2C3_TX.1.Priority=DMA_PRIORITY_LOW
Dma.I2C3_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.MEMTOMEM.2.Direction=DMA_MEMORY_TO_MEMORY
Dma.MEMTOMEM.2.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.MEMTOMEM.2.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.MEMTOMEM.2.Instance=DMA2_Stream0
Dma.MEMTOMEM.2.MemBurst=DMA_MBURST_SINGLE
Dma.MEMTOMEM.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.MEMTOMEM.2.MemInc=DMA_MINC_ENABLE
Dma.MEMTOMEM.2.Mode=DMA_NORMAL
Dma.MEMTOMEM.2.PeriphBurst=DMA_PBURST_SINGLE
Dma.MEMTOMEM.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.MEMTOMEM.2.PeriphInc=DMA_PINC_ENABLE
Dma.MEMTOMEM.2.Priority=DMA_PRIORITY_LOW
Dma.MEMTOMEM.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.Request0=I2C3_RX
Dma.Request1=I2C3_TX
Dma.Request2=MEMTOMEM
Dma.Request3=USART6_RX
Dma.Request4=USART6_TX
Dma.Request5=TIM6_UP
Dma.RequestsNb=6
Dma.TIM6_UP.5.Direction=DMA_PERIPH_TO_MEMORY
Dma.TIM6_UP.5.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.TIM6_UP.5.Instance=DMA1_Stream1
Dma.TIM6_UP.5.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.TIM6_UP.5.MemInc=DMA_MINC_ENABLE
Dma.TIM6_UP.5.Mode=DMA_NORMAL
Dma.TIM6_UP.5.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.TIM6_UP.5.PeriphInc=DMA_PINC_DISABLE
Dma.TIM6_UP.5.Priority=DMA_PRIORITY_LOW
Dma.TIM6_UP.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART6_RX.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART6_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART6_RX.3.Instance=DMA2_Stream1
Dma.USART6_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART6_RX.3.MemInc=DMA_MINC_ENABLE
Dma.USART6_RX.3.Mode=DMA_NORMAL
Dma.USART6_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART6_RX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART6_RX.3.Priority=DMA_PRIORITY_LOW
Dma.USART6_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART6_TX.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART6_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART6_TX.4.Instance=DMA2_Stream6
Dma.USART6_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART6_TX.4.MemInc=DMA_MINC_ENABLE
Dma.USART6_TX.4.Mode=DMA_NORMAL
Dma.USART6_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART6_TX.4.PeriphInc=DMA_PINC_DISABLE
Dma.USART6_TX.4.Priority=DMA_PRIORITY_LOW
Dma.USART6_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
FMC.ExitSelfRefreshDelay1=7
FMC.IPParameters=RowBitsNumber1,CASLatency1,ReadBurst1,ReadBurst2,SDClockPeriod1,SDClockPeriod2,LoadToActiveDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,WriteRecoveryTime1,RPDelay1,RPDelay2,RCDDelay1
FMC.LoadToActiveDelay1=2
FMC.RCDDelay1=2
FMC.RPDelay1=2
FMC.RPDelay2=2
FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE
FMC.RowBitsNumber1=FMC_SDRAM_ROW_BITS_NUM_12
FMC.RowCycleDelay1=6
FMC.RowCycleDelay2=6
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2
FMC.SelfRefreshTime1=4
FMC.WriteRecoveryTime1=2
File.Version=6
I2C3.AddressingMode=I2C_ADDRESSINGMODE_7BIT
I2C3.IPParameters=Timing,AddressingMode,OwnAddress
I2C3.OwnAddress=112
I2C3.Timing=0x00C0EAFF
KeepUserPlacement=true
LTDC.ActiveH=272
LTDC.ActiveW=480
LTDC.HBP=13
LTDC.HFP=32
LTDC.HSync=41
LTDC.IPParameters=ActiveW,ActiveH,HBP,HFP,HSync,VBP,VFP,VSync
LTDC.VBP=2
LTDC.VFP=2
LTDC.VSync=10
Mcu.Family=STM32F7
Mcu.IP0=CORTEX_M7
Mcu.IP1=CRC
Mcu.IP10=TIM6
Mcu.IP11=USART6
Mcu.IP12=USB_DEVICE
Mcu.IP13=USB_OTG_HS
Mcu.IP2=DMA
Mcu.IP3=DMA2D
Mcu.IP4=FMC
Mcu.IP5=I2C3
Mcu.IP6=LTDC
Mcu.IP7=NVIC
Mcu.IP8=RCC
Mcu.IP9=SYS
Mcu.IPNb=14
Mcu.Name=STM32F746N(E-G)Hx
Mcu.Package=TFBGA216
Mcu.Pin0=PE4
Mcu.Pin1=PE3
Mcu.Pin10=PD7
Mcu.Pin100=PJ6
Mcu.Pin101=PD15
Mcu.Pin102=PB13
Mcu.Pin103=PD10
Mcu.Pin104=PF10
Mcu.Pin105=PF9
Mcu.Pin106=PF8
Mcu.Pin107=PC3
Mcu.Pin108=PD14
Mcu.Pin109=PB12
Mcu.Pin11=PC12
Mcu.Pin110=PD9
Mcu.Pin111=PD8
Mcu.Pin112=PC0
Mcu.Pin113=PC1
Mcu.Pin114=PC2
Mcu.Pin115=PB2
Mcu.Pin116=PF12
Mcu.Pin117=PG1
Mcu.Pin118=PF15
Mcu.Pin119=PJ4
Mcu.Pin12=PA15
Mcu.Pin120=PD12
Mcu.Pin121=PD13
Mcu.Pin122=PG3
Mcu.Pin123=PG2
Mcu.Pin124=PJ5
Mcu.Pin125=PH12
Mcu.Pin126=PA1
Mcu.Pin127=PA0/WKUP
Mcu.Pin128=PA4
Mcu.Pin129=PC4
Mcu.Pin13=PA14
Mcu.Pin130=PF13
Mcu.Pin131=PG0
Mcu.Pin132=PJ3
Mcu.Pin133=PE8
Mcu.Pin134=PD11
Mcu.Pin135=PG5
Mcu.Pin136=PG4
Mcu.Pin137=PH7
Mcu.Pin138=PH9
Mcu.Pin139=PH11
Mcu.Pin14=PA13
Mcu.Pin140=PA2
Mcu.Pin141=PA6
Mcu.Pin142=PA5
Mcu.Pin143=PC5
Mcu.Pin144=PF14
Mcu.Pin145=PJ2
Mcu.Pin146=PF11
Mcu.Pin147=PE9
Mcu.Pin148=PE11
Mcu.Pin149=PE14
Mcu.Pin15=PE5
Mcu.Pin150=PB10
Mcu.Pin151=PH6
Mcu.Pin152=PH8
Mcu.Pin153=PH10
Mcu.Pin154=PA3
Mcu.Pin155=PA7
Mcu.Pin156=PB1
Mcu.Pin157=PB0
Mcu.Pin158=PJ0
Mcu.Pin159=PJ1
Mcu.Pin16=PE6
Mcu.Pin160=PE7
Mcu.Pin161=PE10
Mcu.Pin162=PE12
Mcu.Pin163=PE15
Mcu.Pin164=PE13
Mcu.Pin165=PB11
Mcu.Pin166=PB14
Mcu.Pin167=PB15
Mcu.Pin168=VP_CRC_VS_CRC
Mcu.Pin169=VP_DMA2D_VS_DMA2D
Mcu.Pin17=PG13
Mcu.Pin170=VP_SYS_VS_Systick
Mcu.Pin171=VP_TIM6_VS_ClockSourceINT
Mcu.Pin172=VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS
Mcu.Pin18=PB9
Mcu.Pin19=PB7
Mcu.Pin2=PE2
Mcu.Pin20=PB6
Mcu.Pin21=PG15
Mcu.Pin22=PG11
Mcu.Pin23=PJ13
Mcu.Pin24=PJ12
Mcu.Pin25=PD6
Mcu.Pin26=PD0
Mcu.Pin27=PC11
Mcu.Pin28=PC10
Mcu.Pin29=PA12
Mcu.Pin3=PG14
Mcu.Pin30=PI8
Mcu.Pin31=PI4
Mcu.Pin32=PK7
Mcu.Pin33=PK6
Mcu.Pin34=PK5
Mcu.Pin35=PG12
Mcu.Pin36=PG10
Mcu.Pin37=PJ14
Mcu.Pin38=PD5
Mcu.Pin39=PD3
Mcu.Pin4=PE1
Mcu.Pin40=PD1
Mcu.Pin41=PI3
Mcu.Pin42=PI2
Mcu.Pin43=PA11
Mcu.Pin44=PC13
Mcu.Pin45=PF0
Mcu.Pin46=PI5
Mcu.Pin47=PI7
Mcu.Pin48=PI10
Mcu.Pin49=PI6
Mcu.Pin5=PE0
Mcu.Pin50=PK4
Mcu.Pin51=PK3
Mcu.Pin52=PG9
Mcu.Pin53=PJ15
Mcu.Pin54=PD4
Mcu.Pin55=PD2
Mcu.Pin56=PH15
Mcu.Pin57=PI1
Mcu.Pin58=PA10
Mcu.Pin59=PC14/OSC32_IN
Mcu.Pin6=PB8
Mcu.Pin60=PF1
Mcu.Pin61=PI12
Mcu.Pin62=PI9
Mcu.Pin63=PH13
Mcu.Pin64=PH14
Mcu.Pin65=PI0
Mcu.Pin66=PA9
Mcu.Pin67=PC15/OSC32_OUT
Mcu.Pin68=PI11
Mcu.Pin69=PK1
Mcu.Pin7=PB5
Mcu.Pin70=PK2
Mcu.Pin71=PC9
Mcu.Pin72=PA8
Mcu.Pin73=PH0/OSC_IN
Mcu.Pin74=PF2
Mcu.Pin75=PI13
Mcu.Pin76=PI15
Mcu.Pin77=PJ11
Mcu.Pin78=PK0
Mcu.Pin79=PC8
Mcu.Pin8=PB4
Mcu.Pin80=PC7
Mcu.Pin81=PH1/OSC_OUT
Mcu.Pin82=PF3
Mcu.Pin83=PI14
Mcu.Pin84=PH4
Mcu.Pin85=PJ8
Mcu.Pin86=PJ10
Mcu.Pin87=PG8
Mcu.Pin88=PC6
Mcu.Pin89=PF4
Mcu.Pin9=PB3
Mcu.Pin90=PH5
Mcu.Pin91=PH3
Mcu.Pin92=PJ7
Mcu.Pin93=PJ9
Mcu.Pin94=PG7
Mcu.Pin95=PG6
Mcu.Pin96=PF7
Mcu.Pin97=PF6
Mcu.Pin98=PF5
Mcu.Pin99=PH2
Mcu.PinsNb=173
Mcu.UserConstants=
Mcu.UserName=STM32F746NGHx
MxCube.Version=4.15.1
MxDb.Version=DB.4.0.151
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false
NVIC.DMA1_Stream1_IRQn=true\:0\:0\:false\:false\:true
NVIC.DMA1_Stream2_IRQn=true\:0\:0\:false\:false\:true
NVIC.DMA1_Stream4_IRQn=true\:0\:0\:false\:false\:true
NVIC.DMA2_Stream1_IRQn=true\:0\:0\:false\:false\:true
NVIC.DMA2_Stream6_IRQn=true\:0\:0\:false\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false
NVIC.LTDC_IRQn=true\:0\:0\:false\:false\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false
NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true
NVIC.TIM6_DAC_IRQn=true\:0\:0\:false\:false\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false
PA0/WKUP.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PA0/WKUP.GPIO_Label=ARDUINO A0
PA0/WKUP.GPIO_Mode=GPIO_MODE_ANALOG
PA0/WKUP.GPIO_PuPd=GPIO_NOPULL
PA0/WKUP.Locked=true
PA0/WKUP.Signal=ADCx_IN0
PA1.GPIOParameters=GPIO_Label
PA1.GPIO_Label=RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
PA1.Locked=true
PA1.Signal=ETH_REF_CLK
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=OTG_FS_ID
PA10.Locked=true
PA10.Signal=USB_OTG_FS_ID
PA11.GPIOParameters=GPIO_Label
PA11.GPIO_Label=OTG_FS_N
PA11.Locked=true
PA11.Signal=USB_OTG_FS_DM
PA12.GPIOParameters=GPIO_Label
PA12.GPIO_Label=OTG_FS_P
PA12.Locked=true
PA12.Signal=USB_OTG_FS_DP
PA13.GPIOParameters=GPIO_Label
PA13.GPIO_Label=SWDIO
PA13.Locked=true
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.GPIOParameters=GPIO_Label
PA14.GPIO_Label=SWCLK
PA14.Locked=true
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA15.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
PA15.GPIO_Label=ARDUINO PWM/D9
PA15.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
PA15.GPIO_PuPd=GPIO_NOPULL
PA15.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PA15.Locked=true
PA15.Signal=S_TIM2_CH1_ETR
PA2.GPIOParameters=GPIO_Label
PA2.GPIO_Label=RMII_MDIO [LAN8742A-CZ-TR_MDIO]
PA2.Locked=true
PA2.Signal=ETH_MDIO
PA3.GPIOParameters=GPIO_Label
PA3.GPIO_Label=ULPI_D0 [USB3320C-EZK_D0]
PA3.Locked=true
PA3.Mode=Device_HS
PA3.Signal=USB_OTG_HS_ULPI_D0
PA4.GPIOParameters=GPIO_Label
PA4.GPIO_Label=DCMI_HSYNC
PA4.Locked=true
PA4.Signal=DCMI_HSYNC
PA5.GPIOParameters=GPIO_Label
PA5.GPIO_Label=ULPI_CLK [USB3320C-EZK_CLKOUT]
PA5.Locked=true
PA5.Mode=Device_HS
PA5.Signal=USB_OTG_HS_ULPI_CK
PA6.Locked=true
PA6.Signal=DCMI_PIXCLK
PA7.GPIOParameters=GPIO_Label
PA7.GPIO_Label=RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
PA7.Locked=true
PA7.Signal=ETH_CRS_DV
PA8.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
PA8.GPIO_Label=ARDUINO PWM/D5
PA8.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
PA8.GPIO_PuPd=GPIO_NOPULL
PA8.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PA8.Locked=true
PA8.Signal=S_TIM1_CH1
PA9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PA9.GPIO_Label=VCP_TX [STM32F103CBT6_PA3]
PA9.GPIO_Mode=GPIO_MODE_AF_PP
PA9.GPIO_PuPd=GPIO_NOPULL
PA9.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PA9.Locked=true
PA9.Signal=USART1_TX
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=ULPI_D1 [USB3320C-EZK_D1]
PB0.Locked=true
PB0.Mode=Device_HS
PB0.Signal=USB_OTG_HS_ULPI_D1
PB1.GPIOParameters=GPIO_Label
PB1.GPIO_Label=ULPI_D2 [USB3320C-EZK_D2]
PB1.Locked=true
PB1.Mode=Device_HS
PB1.Signal=USB_OTG_HS_ULPI_D2
PB10.GPIOParameters=GPIO_Label
PB10.GPIO_Label=ULPI_D3 [USB3320C-EZK_D3]
PB10.Locked=true
PB10.Mode=Device_HS
PB10.Signal=USB_OTG_HS_ULPI_D3
PB11.GPIOParameters=GPIO_Label
PB11.GPIO_Label=ULPI_D4 [USB3320C-EZK_D4]
PB11.Locked=true
PB11.Mode=Device_HS
PB11.Signal=USB_OTG_HS_ULPI_D4
PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=ULPI_D5 [USB3320C-EZK_D5]
PB12.Locked=true
PB12.Mode=Device_HS
PB12.Signal=USB_OTG_HS_ULPI_D5
PB13.GPIOParameters=GPIO_Label
PB13.GPIO_Label=ULPI_D6 [USB3320C-EZK_D6]
PB13.Locked=true
PB13.Mode=Device_HS
PB13.Signal=USB_OTG_HS_ULPI_D6
PB14.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PB14.GPIO_Label=ARDUINO MISO/D12
PB14.GPIO_Mode=GPIO_MODE_AF_PP
PB14.GPIO_PuPd=GPIO_NOPULL
PB14.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB14.Locked=true
PB14.Signal=SPI2_MISO
PB15.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PB15.GPIO_Label=ARDUINO MOSI/PWM/D11
PB15.GPIO_Mode=GPIO_MODE_AF_PP
PB15.GPIO_PuPd=GPIO_NOPULL
PB15.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB15.Locked=true
PB15.Signal=SPI2_MOSI
PB2.Locked=true
PB2.Signal=QUADSPI_CLK
PB3.GPIOParameters=GPIO_Label
PB3.GPIO_Label=SWO
PB3.Locked=true
PB3.Signal=SYS_JTDO-SWO
PB4.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
PB4.GPIO_Label=ARDUINO PWM/D3
PB4.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
PB4.GPIO_PuPd=GPIO_NOPULL
PB4.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB4.Locked=true
PB4.Signal=S_TIM3_CH1
PB5.GPIOParameters=GPIO_Label
PB5.GPIO_Label=ULPI_D7 [USB3320C-EZK_D7]
PB5.Locked=true
PB5.Mode=Device_HS
PB5.Signal=USB_OTG_HS_ULPI_D7
PB6.GPIOParameters=GPIO_Label
PB6.GPIO_Label=QSPI_NCS [N25Q128A13EF840E_S]
PB6.Locked=true
PB6.Signal=QUADSPI_BK1_NCS
PB7.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PB7.GPIO_Label=VCP_RX [STM32F103CBT6_PA2]
PB7.GPIO_Mode=GPIO_MODE_AF_PP
PB7.GPIO_PuPd=GPIO_NOPULL
PB7.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB7.Locked=true
PB7.Signal=USART1_RX
PB8.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PB8.GPIO_Label=ARDUINO SCL/D15
PB8.GPIO_Mode=GPIO_MODE_AF_OD
PB8.GPIO_PuPd=GPIO_NOPULL
PB8.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB8.Locked=true
PB8.Signal=I2C1_SCL
PB9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PB9.GPIO_Label=ARDUINO SDA/D14
PB9.GPIO_Mode=GPIO_MODE_AF_OD
PB9.GPIO_PuPd=GPIO_NOPULL
PB9.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PB9.Locked=true
PB9.Signal=I2C1_SDA
PC0.GPIOParameters=GPIO_Label
PC0.GPIO_Label=ULPI_STP [USB3320C-EZK_STP]
PC0.Locked=true
PC0.Mode=Device_HS
PC0.Signal=USB_OTG_HS_ULPI_STP
PC1.GPIOParameters=GPIO_Label
PC1.GPIO_Label=RMII_MDC [LAN8742A-CZ-TR_MDC]
PC1.Locked=true
PC1.Signal=ETH_MDC
PC10.GPIOParameters=GPIO_Label
PC10.GPIO_Label=SDMMC_D2
PC10.Locked=true
PC10.Signal=SDMMC1_D2
PC11.GPIOParameters=GPIO_Label
PC11.GPIO_Label=SDMMC_D3
PC11.Locked=true
PC11.Signal=SDMMC1_D3
PC12.GPIOParameters=GPIO_Label
PC12.GPIO_Label=SDMMC_CK
PC12.Locked=true
PC12.Signal=SDMMC1_CK
PC13.GPIOParameters=GPIO_Label
PC13.GPIO_Label=uSD_Detect
PC13.Locked=true
PC13.Signal=GPIO_Input
PC14/OSC32_IN.GPIOParameters=GPIO_Label
PC14/OSC32_IN.GPIO_Label=RCC_OSC32_IN
PC14/OSC32_IN.Locked=true
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.GPIOParameters=GPIO_Label
PC15/OSC32_OUT.GPIO_Label=RCC_OSC32_OUT
PC15/OSC32_OUT.Locked=true
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.GPIOParameters=GPIO_Label
PC2.GPIO_Label=ULPI_DIR [USB3320C-EZK_DIR]
PC2.Locked=true
PC2.Mode=Device_HS
PC2.Signal=USB_OTG_HS_ULPI_DIR
PC3.GPIOParameters=GPIO_Label
PC3.GPIO_Label=FMC_SDCKE0 [MT48LC4M32B2B5-6A_CKE]
PC3.Locked=true
PC3.Mode=SdramChipSelect1_1
PC3.Signal=FMC_SDCKE0
PC4.GPIOParameters=GPIO_Label
PC4.GPIO_Label=RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
PC4.Locked=true
PC4.Signal=ETH_RXD0
PC5.GPIOParameters=GPIO_Label
PC5.GPIO_Label=RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
PC5.Locked=true
PC5.Signal=ETH_RXD1
PC6.GPIOParameters=GPIO_Label
PC6.GPIO_Label=ARDUINO TX/D1
PC6.Locked=true
PC6.Mode=Asynchronous
PC6.Signal=USART6_TX
PC7.GPIOParameters=GPIO_Label
PC7.GPIO_Label=ARDUINO RX/D0
PC7.Locked=true
PC7.Mode=Asynchronous
PC7.Signal=USART6_RX
PC8.Locked=true
PC8.Signal=SDMMC1_D0
PC9.Locked=true
PC9.Signal=SDMMC1_D1
PCC.Checker=false
PCC.Line=STM32F7x6
PCC.MCU=STM32F746N(E-G)Hx
PCC.MXVersion=4.15.1
PCC.PartNumber=STM32F746NGHx
PCC.Seq0=0
PCC.Series=STM32F7
PCC.Temperature=25
PCC.Vdd=3.3
PD0.GPIOParameters=GPIO_Label
PD0.GPIO_Label=FMC_D2 [MT48LC4M32B2B5-6A_DQ2]
PD0.Locked=true
PD0.Signal=FMC_D2_DA2
PD1.GPIOParameters=GPIO_Label
PD1.GPIO_Label=FMC_D3 [MT48LC4M32B2B5-6A_DQ3]
PD1.Locked=true
PD1.Signal=FMC_D3_DA3
PD10.GPIOParameters=GPIO_Label
PD10.GPIO_Label=FMC_D15 [MT48LC4M32B2B5-6A_DQ15]
PD10.Locked=true
PD10.Signal=FMC_D15_DA15
PD11.GPIOParameters=GPIO_Label
PD11.GPIO_Label=QSPI_D0 [N25Q128A13EF840E_DQ0]
PD11.Locked=true
PD11.Signal=QUADSPI_BK1_IO0
PD12.GPIOParameters=GPIO_Label
PD12.GPIO_Label=QSPI_D1 [N25Q128A13EF840E_DQ1]
PD12.Locked=true
PD12.Signal=QUADSPI_BK1_IO1
PD13.GPIOParameters=GPIO_Label
PD13.GPIO_Label=QSPI_D3 [N25Q128A13EF840E_DQ3]
PD13.Locked=true
PD13.Signal=QUADSPI_BK1_IO3
PD14.GPIOParameters=GPIO_Label
PD14.GPIO_Label=FMC_D0 [MT48LC4M32B2B5-6A_DQ0]
PD14.Locked=true
PD14.Signal=FMC_D0_DA0
PD15.GPIOParameters=GPIO_Label
PD15.GPIO_Label=FMC_D1 [MT48LC4M32B2B5-6A_DQ1]
PD15.Locked=true
PD15.Signal=FMC_D1_DA1
PD2.GPIOParameters=GPIO_Label
PD2.GPIO_Label=SDMMC_D0
PD2.Locked=true
PD2.Signal=SDMMC1_CMD
PD3.GPIOParameters=GPIO_Label
PD3.GPIO_Label=DCMI_D5
PD3.Locked=true
PD3.Signal=DCMI_D5
PD4.GPIOParameters=GPIO_Label
PD4.GPIO_Label=OTG_FS_OverCurrent [STMPS2141STR_Fault]
PD4.Locked=true
PD4.Signal=GPIO_Input
PD5.GPIOParameters=GPIO_Label
PD5.GPIO_Label=OTG_FS_PowerSwitchOn [STMPS2141STR_EN]
PD5.Locked=true
PD5.Signal=GPIO_Output
PD6.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
PD6.GPIO_Label=Audio_INT
PD6.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING
PD6.Locked=true
PD6.Signal=GPXTI6
PD7.GPIOParameters=GPIO_Label
PD7.GPIO_Label=SPDIF_RX0 [74LVC1G04SE_4]
PD7.Locked=true
PD7.Signal=SPDIFRX_IN0
PD8.GPIOParameters=GPIO_Label
PD8.GPIO_Label=FMC_D13 [MT48LC4M32B2B5-6A_DQ13]
PD8.Locked=true
PD8.Signal=FMC_D13_DA13
PD9.GPIOParameters=GPIO_Label
PD9.GPIO_Label=FMC_D14 [MT48LC4M32B2B5-6A_DQ14]
PD9.Locked=true
PD9.Signal=FMC_D14_DA14
PE0.GPIOParameters=GPIO_Label
PE0.GPIO_Label=FMC_NBL0 [MT48LC4M32B2B5-6A_DQM0]
PE0.Locked=true
PE0.Signal=FMC_NBL0
PE1.GPIOParameters=GPIO_Label
PE1.GPIO_Label=FMC_NBL1 [MT48LC4M32B2B5-6A_DQM1]
PE1.Locked=true
PE1.Signal=FMC_NBL1
PE10.GPIOParameters=GPIO_Label
PE10.GPIO_Label=FMC_D7 [MT48LC4M32B2B5-6A_DQ7]
PE10.Locked=true
PE10.Signal=FMC_D7_DA7
PE11.GPIOParameters=GPIO_Label
PE11.GPIO_Label=FMC_D8 [MT48LC4M32B2B5-6A_DQ8]
PE11.Locked=true
PE11.Signal=FMC_D8_DA8
PE12.GPIOParameters=GPIO_Label
PE12.GPIO_Label=FMC_D9 [MT48LC4M32B2B5-6A_DQ9]
PE12.Locked=true
PE12.Signal=FMC_D9_DA9
PE13.GPIOParameters=GPIO_Label
PE13.GPIO_Label=FMC_D10 [MT48LC4M32B2B5-6A_DQ10]
PE13.Locked=true
PE13.Signal=FMC_D10_DA10
PE14.GPIOParameters=GPIO_Label
PE14.GPIO_Label=FMC_D11 [MT48LC4M32B2B5-6A_DQ11]
PE14.Locked=true
PE14.Signal=FMC_D11_DA11
PE15.GPIOParameters=GPIO_Label
PE15.GPIO_Label=FMC_D12 [MT48LC4M32B2B5-6A_DQ12]
PE15.Locked=true
PE15.Signal=FMC_D12_DA12
PE2.GPIOParameters=GPIO_Label
PE2.GPIO_Label=QSPI_D2 [N25Q128A13EF840E_DQ2]
PE2.Locked=true
PE2.Signal=QUADSPI_BK1_IO2
PE3.GPIOParameters=GPIO_Label
PE3.GPIO_Label=OTG_HS_OverCurrent [STMPS2151STR_FAULT]
PE3.Locked=true
PE3.Signal=GPIO_Input
PE4.GPIOParameters=GPIO_Label
PE4.GPIO_Label=LCD_B0 [RK043FN48H-CT672B_B0]
PE4.Locked=true
PE4.Mode=RGB888
PE4.Signal=LTDC_B0
PE5.GPIOParameters=GPIO_Label
PE5.GPIO_Label=DCMI_D6
PE5.Locked=true
PE5.Signal=DCMI_D6
PE6.GPIOParameters=GPIO_Label
PE6.GPIO_Label=DCMI_D7
PE6.Locked=true
PE6.Signal=DCMI_D7
PE7.GPIOParameters=GPIO_Label
PE7.GPIO_Label=FMC_D4 [MT48LC4M32B2B5-6A_DQ4]
PE7.Locked=true
PE7.Signal=FMC_D4_DA4
PE8.GPIOParameters=GPIO_Label
PE8.GPIO_Label=FMC_D5 [MT48LC4M32B2B5-6A_DQ5]
PE8.Locked=true
PE8.Signal=FMC_D5_DA5
PE9.GPIOParameters=GPIO_Label
PE9.GPIO_Label=FMC_D6 [MT48LC4M32B2B5-6A_DQ6]
PE9.Locked=true
PE9.Signal=FMC_D6_DA6
PF0.GPIOParameters=GPIO_Label
PF0.GPIO_Label=FMC_A0 [MT48LC4M32B2B5-6A_A0]
PF0.Locked=true
PF0.Signal=FMC_A0
PF1.GPIOParameters=GPIO_Label
PF1.GPIO_Label=FMC_A1 [MT48LC4M32B2B5-6A_A1]
PF1.Locked=true
PF1.Signal=FMC_A1
PF10.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PF10.GPIO_Label=ARDUINO A1
PF10.GPIO_Mode=GPIO_MODE_ANALOG
PF10.GPIO_PuPd=GPIO_NOPULL
PF10.Locked=true
PF10.Signal=ADC3_IN8
PF11.GPIOParameters=GPIO_Label
PF11.GPIO_Label=FMC_SDNRAS [MT48LC4M32B2B5-6A_RAS]
PF11.Locked=true
PF11.Signal=FMC_SDNRAS
PF12.GPIOParameters=GPIO_Label
PF12.GPIO_Label=FMC_A6 [MT48LC4M32B2B5-6A_A6]
PF12.Locked=true
PF12.Signal=FMC_A6
PF13.GPIOParameters=GPIO_Label
PF13.GPIO_Label=FMC_A7 [MT48LC4M32B2B5-6A_A7]
PF13.Locked=true
PF13.Signal=FMC_A7
PF14.GPIOParameters=GPIO_Label
PF14.GPIO_Label=FMC_A8 [MT48LC4M32B2B5-6A_A8]
PF14.Locked=true
PF14.Signal=FMC_A8
PF15.GPIOParameters=GPIO_Label
PF15.GPIO_Label=FMC_A9 [MT48LC4M32B2B5-6A_A9]
PF15.Locked=true
PF15.Signal=FMC_A9
PF2.GPIOParameters=GPIO_Label
PF2.GPIO_Label=FMC_A2 [MT48LC4M32B2B5-6A_A2]
PF2.Locked=true
PF2.Signal=FMC_A2
PF3.GPIOParameters=GPIO_Label
PF3.GPIO_Label=FMC_A3 [MT48LC4M32B2B5-6A_A3]
PF3.Locked=true
PF3.Signal=FMC_A3
PF4.GPIOParameters=GPIO_Label
PF4.GPIO_Label=FMC_A4 [MT48LC4M32B2B5-6A_A4]
PF4.Locked=true
PF4.Signal=FMC_A4
PF5.GPIOParameters=GPIO_Label
PF5.GPIO_Label=FMC_A5 [MT48LC4M32B2B5-6A_A5]
PF5.Locked=true
PF5.Signal=FMC_A5
PF6.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PF6.GPIO_Label=ARDUINO A5
PF6.GPIO_Mode=GPIO_MODE_ANALOG
PF6.GPIO_PuPd=GPIO_NOPULL
PF6.Locked=true
PF6.Signal=ADC3_IN4
PF7.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PF7.GPIO_Label=ARDUINO A4
PF7.GPIO_Mode=GPIO_MODE_ANALOG
PF7.GPIO_PuPd=GPIO_NOPULL
PF7.Locked=true
PF7.Signal=ADC3_IN5
PF8.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PF8.GPIO_Label=ARDUINO A3
PF8.GPIO_Mode=GPIO_MODE_ANALOG
PF8.GPIO_PuPd=GPIO_NOPULL
PF8.Locked=true
PF8.Signal=ADC3_IN6
PF9.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_Mode
PF9.GPIO_Label=ARDUINO A2
PF9.GPIO_Mode=GPIO_MODE_ANALOG
PF9.GPIO_PuPd=GPIO_NOPULL
PF9.Locked=true
PF9.Signal=ADC3_IN7
PG0.GPIOParameters=GPIO_Label
PG0.GPIO_Label=FMC_A10 [MT48LC4M32B2B5-6A_A10]
PG0.Locked=true
PG0.Signal=FMC_A10
PG1.GPIOParameters=GPIO_Label
PG1.GPIO_Label=FMC_A11 [MT48LC4M32B2B5-6A_A11]
PG1.Locked=true
PG1.Signal=FMC_A11
PG10.GPIOParameters=GPIO_Label
PG10.GPIO_Label=SAI2_SDB [WM8994ECS/R_ADCDAT1]
PG10.Locked=true
PG10.Signal=SAI2_SD_B
PG11.GPIOParameters=GPIO_Label
PG11.GPIO_Label=RMII_TX_EN [LAN8742A-CZ-TR_TXEN]
PG11.Locked=true
PG11.Signal=ETH_TX_EN
PG12.GPIOParameters=GPIO_Label
PG12.GPIO_Label=LCD_B4 [RK043FN48H-CT672B_B4]
PG12.Locked=true
PG12.Mode=RGB888
PG12.Signal=LTDC_B4
PG13.GPIOParameters=GPIO_Label
PG13.GPIO_Label=RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
PG13.Locked=true
PG13.Signal=ETH_TXD0
PG14.GPIOParameters=GPIO_Label
PG14.GPIO_Label=RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
PG14.Locked=true
PG14.Signal=ETH_TXD1
PG15.GPIOParameters=GPIO_Label
PG15.GPIO_Label=FMC_SDNCAS [MT48LC4M32B2B5-6A_CAS]
PG15.Locked=true
PG15.Signal=FMC_SDNCAS
PG2.GPIOParameters=GPIO_Label
PG2.GPIO_Label=RMII_RXER
PG2.Locked=true
PG2.Signal=GPIO_Input
PG3.GPIOParameters=GPIO_Label
PG3.GPIO_Label=EXT_RST
PG3.Locked=true
PG3.Signal=GPIO_Output
PG4.GPIOParameters=GPIO_Label
PG4.GPIO_Label=FMC_BA0 [MT48LC4M32B2B5-6A_BA0]
PG4.Locked=true
PG4.Signal=FMC_A14_BA0
PG5.GPIOParameters=GPIO_Label
PG5.GPIO_Label=FMC_BA1 [MT48LC4M32B2B5-6A_BA1]
PG5.Locked=true
PG5.Signal=FMC_A15_BA1
PG6.GPIOParameters=GPIO_Label
PG6.GPIO_Label=ARDUINO D2
PG6.Locked=true
PG6.Signal=GPIO_Output
PG7.GPIOParameters=GPIO_Label
PG7.GPIO_Label=ARDUINO D4
PG7.Locked=true
PG7.Signal=GPIO_Output
PG8.GPIOParameters=GPIO_Label
PG8.GPIO_Label=FMC_SDCLK [MT48LC4M32B2B5-6A_CLK]
PG8.Locked=true
PG8.Signal=FMC_SDCLK
PG9.GPIOParameters=GPIO_Label
PG9.GPIO_Label=DCMI_VSYNC
PG9.Locked=true
PG9.Signal=DCMI_VSYNC
PH0/OSC_IN.GPIOParameters=GPIO_Label
PH0/OSC_IN.GPIO_Label=OSC_25M [NZ2520SB-25.00M_OUT]
PH0/OSC_IN.Locked=true
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Locked=true
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PH10.GPIOParameters=GPIO_Label
PH10.GPIO_Label=DCMI_D1
PH10.Locked=true
PH10.Signal=DCMI_D1
PH11.GPIOParameters=GPIO_Label
PH11.GPIO_Label=DCMI_D2
PH11.Locked=true
PH11.Signal=DCMI_D2
PH12.GPIOParameters=GPIO_Label
PH12.GPIO_Label=DCMI_D3
PH12.Locked=true
PH12.Signal=DCMI_D3
PH13.GPIOParameters=GPIO_Label
PH13.GPIO_Label=DCMI_PWR_EN
PH13.Locked=true
PH13.Signal=GPIO_Output
PH14.GPIOParameters=GPIO_Label
PH14.GPIO_Label=DCMI_D4
PH14.Locked=true
PH14.Signal=DCMI_D4
PH15.GPIOParameters=GPIO_Label
PH15.GPIO_Label=TP3
PH15.Locked=true
PH15.Signal=GPIO_Input
PH2.GPIOParameters=GPIO_Label
PH2.GPIO_Label=NC2
PH2.Locked=true
PH2.Signal=GPIO_Input
PH3.GPIOParameters=GPIO_Label
PH3.GPIO_Label=FMC_SDNE0 [MT48LC4M32B2B5-6A_CS]
PH3.Locked=true
PH3.Mode=SdramChipSelect1_1
PH3.Signal=FMC_SDNE0
PH4.GPIOParameters=GPIO_Label
PH4.GPIO_Label=ULPI_NXT [USB3320C-EZK_NXT]
PH4.Locked=true
PH4.Mode=Device_HS
PH4.Signal=USB_OTG_HS_ULPI_NXT
PH5.GPIOParameters=GPIO_Label
PH5.GPIO_Label=FMC_SDNME [MT48LC4M32B2B5-6A_WE]
PH5.Locked=true
PH5.Signal=FMC_SDNWE
PH6.GPIOParameters=GPIO_Label
PH6.GPIO_Label=ARDUINO PWM/D6
PH6.Locked=true
PH6.Signal=S_TIM12_CH1
PH7.GPIOParameters=GPIO_Label
PH7.GPIO_Label=LCD_SCL [RK043FN48H-CT672B_SCL]
PH7.Locked=true
PH7.Mode=I2C
PH7.Signal=I2C3_SCL
PH8.GPIOParameters=GPIO_Label
PH8.GPIO_Label=LCD_SDA [RK043FN48H-CT672B_SDA]
PH8.Locked=true
PH8.Mode=I2C
PH8.Signal=I2C3_SDA
PH9.GPIOParameters=GPIO_Label
PH9.GPIO_Label=DCMI_D0
PH9.Locked=true
PH9.Signal=DCMI_D0
PI0.GPIOParameters=GPIO_ModeDefaultPP,GPIO_Speed,GPIO_PuPd,GPIO_Label
PI0.GPIO_Label=ARDUINO PWM/CS/D10
PI0.GPIO_ModeDefaultPP=GPIO_MODE_AF_PP
PI0.GPIO_PuPd=GPIO_NOPULL
PI0.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PI0.Locked=true
PI0.Signal=S_TIM5_CH4
PI1.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode
PI1.GPIO_Label=ARDUINO SCK/D13
PI1.GPIO_Mode=GPIO_MODE_AF_PP
PI1.GPIO_PuPd=GPIO_NOPULL
PI1.GPIO_Speed=GPIO_SPEED_FREQ_LOW
PI1.Locked=true
PI1.Signal=SPI2_SCK
PI10.GPIOParameters=GPIO_Label
PI10.GPIO_Label=LCD_HSYNC [RK043FN48H-CT672B_HSYNC]
PI10.Locked=true
PI10.Mode=RGB888
PI10.Signal=LTDC_HSYNC
PI11.Mode=SYS_WakeUp5
PI11.Signal=SYS_WKUP6
PI12.GPIOParameters=GPIO_Label
PI12.GPIO_Label=LCD_DISP [RK043FN48H-CT672B_DISP] 
PI12.Locked=true
PI12.Signal=GPIO_Output
PI13.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
PI13.GPIO_Label=LCD_INT
PI13.GPIO_ModeDefaultEXTI=GPIO_MODE_EVT_RISING
PI13.Locked=true
PI13.Signal=GPXTI13
PI14.GPIOParameters=GPIO_Label
PI14.GPIO_Label=LCD_CLK [RK043FN48H-CT672B_CLK]
PI14.Locked=true
PI14.Mode=RGB888
PI14.Signal=LTDC_CLK
PI15.GPIOParameters=GPIO_Label
PI15.GPIO_Label=LCD_R0 [RK043FN48H-CT672B_R0]
PI15.Locked=true
PI15.Mode=RGB888
PI15.Signal=LTDC_R0
PI2.GPIOParameters=GPIO_Label
PI2.GPIO_Label=ARDUINO D8
PI2.Locked=true
PI2.Signal=GPIO_Output
PI3.GPIOParameters=GPIO_Label
PI3.GPIO_Label=ARDUINO D7
PI3.Locked=true
PI3.Signal=GPIO_Output
PI4.GPIOParameters=GPIO_Label
PI4.GPIO_Label=SAI2_MCLKA [WM8994ECS/R_MCLK1]
PI4.Locked=true
PI4.Signal=SAI2_MCLK_A
PI5.GPIOParameters=GPIO_Label
PI5.GPIO_Label=SAI2_SCKA [WM8994ECS/R_BCLK1]
PI5.Locked=true
PI5.Signal=SAI2_SCK_A
PI6.GPIOParameters=GPIO_Label
PI6.GPIO_Label=SAI2_SDA [WM8994ECS/R_DACDAT1]
PI6.Locked=true
PI6.Signal=SAI2_SD_A
PI7.GPIOParameters=GPIO_Label
PI7.GPIO_Label=SAI2_FSA [WM8994ECS/R_LRCLK1]
PI7.Locked=true
PI7.Signal=SAI2_FS_A
PI8.GPIOParameters=GPIO_Label
PI8.GPIO_Label=NC1 [TP2]
PI8.Locked=true
PI8.Signal=RTC_TS
PI9.GPIOParameters=GPIO_Label
PI9.GPIO_Label=LCD_VSYNC [RK043FN48H-CT672B_VSYNC]
PI9.Locked=true
PI9.Mode=RGB888
PI9.Signal=LTDC_VSYNC
PJ0.GPIOParameters=GPIO_Label
PJ0.GPIO_Label=LCD_R1 [RK043FN48H-CT672B_R1]
PJ0.Locked=true
PJ0.Mode=RGB888
PJ0.Signal=LTDC_R1
PJ1.GPIOParameters=GPIO_Label
PJ1.GPIO_Label=LCD_R2 [RK043FN48H-CT672B_R2]
PJ1.Locked=true
PJ1.Mode=RGB888
PJ1.Signal=LTDC_R2
PJ10.GPIOParameters=GPIO_Label
PJ10.GPIO_Label=LCD_G3 [RK043FN48H-CT672B_G3]
PJ10.Locked=true
PJ10.Mode=RGB888
PJ10.Signal=LTDC_G3
PJ11.GPIOParameters=GPIO_Label
PJ11.GPIO_Label=LCD_G4 [RK043FN48H-CT672B_G4]
PJ11.Locked=true
PJ11.Mode=RGB888
PJ11.Signal=LTDC_G4
PJ12.GPIOParameters=GPIO_Label
PJ12.GPIO_Label=OTG_FS_VBUS
PJ12.Locked=true
PJ12.Signal=GPIO_Input
PJ13.GPIOParameters=GPIO_Label
PJ13.GPIO_Label=LCD_B1 [RK043FN48H-CT672B_B1]
PJ13.Locked=true
PJ13.Mode=RGB888
PJ13.Signal=LTDC_B1
PJ14.GPIOParameters=GPIO_Label
PJ14.GPIO_Label=LCD_B2 [RK043FN48H-CT672B_B2]
PJ14.Locked=true
PJ14.Mode=RGB888
PJ14.Signal=LTDC_B2
PJ15.GPIOParameters=GPIO_Label
PJ15.GPIO_Label=LCD_B3 [RK043FN48H-CT672B_B3]
PJ15.Locked=true
PJ15.Mode=RGB888
PJ15.Signal=LTDC_B3
PJ2.GPIOParameters=GPIO_Label
PJ2.GPIO_Label=LCD_R3 [RK043FN48H-CT672B_R3]
PJ2.Locked=true
PJ2.Mode=RGB888
PJ2.Signal=LTDC_R3
PJ3.GPIOParameters=GPIO_Label
PJ3.GPIO_Label=LCD_R4 [RK043FN48H-CT672B_R4]
PJ3.Locked=true
PJ3.Mode=RGB888
PJ3.Signal=LTDC_R4
PJ4.GPIOParameters=GPIO_Label
PJ4.GPIO_Label=LCD_R5 [RK043FN48H-CT672B_R5]
PJ4.Locked=true
PJ4.Mode=RGB888
PJ4.Signal=LTDC_R5
PJ5.GPIOParameters=GPIO_Label
PJ5.GPIO_Label=LCD_R6 [RK043FN48H-CT672B_R6]
PJ5.Locked=true
PJ5.Mode=RGB888
PJ5.Signal=LTDC_R6
PJ6.GPIOParameters=GPIO_Label
PJ6.GPIO_Label=LCD_R7 [RK043FN48H-CT672B_R7]
PJ6.Locked=true
PJ6.Mode=RGB888
PJ6.Signal=LTDC_R7
PJ7.GPIOParameters=GPIO_Label
PJ7.GPIO_Label=LCD_G0 [RK043FN48H-CT672B_G0]
PJ7.Locked=true
PJ7.Mode=RGB888
PJ7.Signal=LTDC_G0
PJ8.GPIOParameters=GPIO_Label
PJ8.GPIO_Label=LCD_G1 [RK043FN48H-CT672B_G1]
PJ8.Locked=true
PJ8.Mode=RGB888
PJ8.Signal=LTDC_G1
PJ9.GPIOParameters=GPIO_Label
PJ9.GPIO_Label=LCD_G2 [RK043FN48H-CT672B_G2]
PJ9.Locked=true
PJ9.Mode=RGB888
PJ9.Signal=LTDC_G2
PK0.GPIOParameters=GPIO_Label
PK0.GPIO_Label=LCD_G5 [RK043FN48H-CT672B_G5]
PK0.Locked=true
PK0.Mode=RGB888
PK0.Signal=LTDC_G5
PK1.GPIOParameters=GPIO_Label
PK1.GPIO_Label=LCD_G6 [RK043FN48H-CT672B_G6]
PK1.Locked=true
PK1.Mode=RGB888
PK1.Signal=LTDC_G6
PK2.GPIOParameters=GPIO_Label
PK2.GPIO_Label=LCD_G7 [RK043FN48H-CT672B_G7]
PK2.Locked=true
PK2.Mode=RGB888
PK2.Signal=LTDC_G7
PK3.GPIOParameters=GPIO_Label
PK3.GPIO_Label=LCD_BL_CTRL [STLD40DPUR_EN]
PK3.Locked=true
PK3.Signal=GPIO_Output
PK4.GPIOParameters=GPIO_Label
PK4.GPIO_Label=LCD_B5 [RK043FN48H-CT672B_B5]
PK4.Locked=true
PK4.Mode=RGB888
PK4.Signal=LTDC_B5
PK5.GPIOParameters=GPIO_Label
PK5.GPIO_Label=LCD_B6 [RK043FN48H-CT672B_B6]
PK5.Locked=true
PK5.Mode=RGB888
PK5.Signal=LTDC_B6
PK6.GPIOParameters=GPIO_Label
PK6.GPIO_Label=LCD_B7 [RK043FN48H-CT672B_B7]
PK6.Locked=true
PK6.Mode=RGB888
PK6.Signal=LTDC_B7
PK7.GPIOParameters=GPIO_Label
PK7.GPIO_Label=LCD_DE [RK043FN48H-CT672B_DE]
PK7.Locked=true
PK7.Mode=RGB888
PK7.Signal=LTDC_DE
RCC.AHBFreq_Value=200000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=50000000
RCC.APB1TimFreq_Value=100000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=100000000
RCC.APB2TimFreq_Value=200000000
RCC.CECFreq_Value=32786.88524590164
RCC.CortexFreq_Value=200000000
RCC.EthernetFreq_Value=200000000
RCC.FCLKCortexFreq_Value=200000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=200000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=50000000
RCC.I2C2Freq_Value=50000000
RCC.I2C3Freq_Value=50000000
RCC.I2C4Freq_Value=50000000
RCC.I2SFreq_Value=104166666.66666666
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO2PinFreq_Value,PLL48CLockSelection,PLLCLKFreq_Value,PLLI2SN,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIP,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIR,PLLSAIRCLKFreq_Value,PLLSAIRDiv,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFToutputFreq_Value=20000000
RCC.LPTIM1Freq_Value=50000000
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=200000000
RCC.PLL48CLockSelection=RCC_CLK48SOURCE_PLLSAIP
RCC.PLLCLKFreq_Value=200000000
RCC.PLLI2SN=100
RCC.PLLI2SPCLKFreq_Value=104166666.66666666
RCC.PLLI2SQCLKFreq_Value=104166666.66666666
RCC.PLLI2SRCLKFreq_Value=104166666.66666666
RCC.PLLI2SRoutputFreq_Value=104166666.66666666
RCC.PLLM=12
RCC.PLLQ=8
RCC.PLLQCLKFreq_Value=50000000
RCC.PLLQoutputFreq_Value=50000000
RCC.PLLSAIP=RCC_PLLSAIP_DIV4
RCC.PLLSAIPCLKFreq_Value=100000000
RCC.PLLSAIQCLKFreq_Value=200000000
RCC.PLLSAIR=5
RCC.PLLSAIRCLKFreq_Value=80000000
RCC.PLLSAIRDiv=RCC_PLLSAIDIVR_4
RCC.PLLSAIoutputFreq_Value=100000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RNGFreq_Value=100000000
RCC.SAI1Freq_Value=200000000
RCC.SAI2Freq_Value=200000000
RCC.SDMMCFreq_Value=200000000
RCC.SPDIFRXFreq_Value=104166666.66666666
RCC.SYSCLKFreq_VALUE=200000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=50000000
RCC.UART5Freq_Value=50000000
RCC.UART7Freq_Value=50000000
RCC.UART8Freq_Value=50000000
RCC.USART1Freq_Value=100000000
RCC.USART2Freq_Value=50000000
RCC.USART3Freq_Value=50000000
RCC.USART6Freq_Value=100000000
RCC.USBFreq_Value=100000000
RCC.VCOI2SOutputFreq_Value=208333333.3333333
RCC.VCOInputFreq_Value=2083333.3333333333
RCC.VCOOutputFreq_Value=400000000
RCC.VCOSAIOutputFreq_Value=400000000
SH.ADCx_IN0.0=ADC3_IN0
SH.ADCx_IN0.ConfNb=1
SH.FMC_A0.0=FMC_A0,12b-sda1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,12b-sda1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,12b-sda1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,12b-sda1
SH.FMC_A11.ConfNb=1
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A2.0=FMC_A2,12b-sda1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,12b-sda1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,12b-sda1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,12b-sda1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,12b-sda1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,12b-sda1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,12b-sda1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,12b-sda1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
SH.FMC_NBL0.ConfNb=1
SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
SH.FMC_NBL1.ConfNb=1
SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
SH.FMC_SDCLK.ConfNb=1
SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
SH.FMC_SDNCAS.ConfNb=1
SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
SH.FMC_SDNRAS.ConfNb=1
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
SH.FMC_SDNWE.ConfNb=1
SH.GPXTI13.0=GPIO_EXTI13
SH.GPXTI13.ConfNb=1
SH.GPXTI6.0=GPIO_EXTI6
SH.GPXTI6.ConfNb=1
SH.S_TIM12_CH1.0=TIM12_CH1
SH.S_TIM12_CH1.ConfNb=1
SH.S_TIM1_CH1.0=TIM1_CH1
SH.S_TIM1_CH1.ConfNb=1
SH.S_TIM2_CH1_ETR.0=TIM2_CH1
SH.S_TIM2_CH1_ETR.ConfNb=1
SH.S_TIM3_CH1.0=TIM3_CH1
SH.S_TIM3_CH1.ConfNb=1
SH.S_TIM5_CH4.0=TIM5_CH4
SH.S_TIM5_CH4.ConfNb=1
TIM6.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger
TIM6.Period=500
TIM6.Prescaler=10000
TIM6.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
USART6.IPParameters=WordLength
USART6.WordLength=UART_WORDLENGTH_8B
USB_DEVICE.CLASS_NAME-CDC_HS=CDC
USB_DEVICE.CLASS_NAME_HS=CDC
USB_DEVICE.IPParameters=VirtualMode-CDC_HS,VirtualModeHS,USBD_HandleTypeDef-CDC_HS,CLASS_NAME-CDC_HS,CLASS_NAME_HS
USB_DEVICE.USBD_HandleTypeDef-CDC_HS=hUsbDeviceHS
USB_DEVICE.VirtualMode-CDC_HS=Cdc
USB_DEVICE.VirtualModeHS=Cdc_HS
USB_OTG_HS.IPParameters=VirtualMode-Device_HS
USB_OTG_HS.VirtualMode-Device_HS=Device_HS
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
VP_TIM6_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM6_VS_ClockSourceINT.Signal=TIM6_VS_ClockSourceINT
VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Mode=CDC_HS
VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_HS
board=STM32F746G-DISCO
boardIOC=true